1. Field of the Invention
This invention relates generally to the cell structure and fabrication process of vertical power transistors. More particularly, this invention relates to switching speed improvement achieved by carrying out a high-energy body-conductivity-type-dopant implant, e.g., boron implant through the gate. The high-energy body-conductivity-type-dopant implant forms a reduced doping concentration zone, e.g., an n zone, under the gate that serves to reduce the gate-to-drain capacitance of a vertical DMOS planar device. Thus, the device switching speed is improved with the reduced gate-to-drain capacitance without significantly increasing the on-resistance.
2. Description of the Prior Art
Improvement of the switching speed of a low-voltage DMOS power device cannot be conveniently achieved for the reason that the epitaxial layer is formed to have a low resistivity. A low resitivity is of course a desirable design feature for the low voltage device as a typical prior art device 10 shown in FIG. 1. However, an epitaxial layer 15 with a low resistivity as shown often causes a high capacitance between the gate 20 and the drain 15. As will be further described below, the switching speed of the DMOS device 10 is adversely affected by a high gate-to-drain capacitance.
FIG. 1B is an equivalent circuit diagram of the parasitic capacitors between the gate 20 and the drain 15. There is a first parasitic capacitor Cox formed over the gate oxide, which is connected in series to a second parasitic capacitor Cdepl formed over a depletion layer underneath the gate oxide layer. The gate-to-drain capacitance as a total capacitance over these two parasitic capacitors is:
Cgd=(CoxCdepl)/[Cox+Cdepl]xe2x80x83xe2x80x83(1)
Where the capacitance of the parasitic capacitor over a depletion layer is inversely proportional the thickness of the depletion layer tdepl where a positive bias voltage is applied between drain and gate.
Cdepl=K/tdeplxe2x80x83xe2x80x83(2)
Where K is a constant. The thickness of the depletion layer tdepl is inversely proportional to the square root of the dopant concentration, therefore:
Cdepl=K(Nepi)1/2xe2x80x83xe2x80x83(3)
Where Nepi represents the dopant concentration of the source epitaxial region 15. It can be derived from Equations (3) that by reducing the dopant concentration of the epitaxial layer, i.e., Nepi the capacitance over the depletion layer Cepi is reduced. And, from Equation (2), it is also clear that the gate-to-drain capacitance CGD is also reduced. A relationship between the capacitance CGD and that of the Nepi is shown in FIG. 1C. A technique to improve the device switching speed is to reduce the dopant concentration in the Nepi layer. However, a lower dopant concentration under the gate often causes the on-resistance to increase. Also, if the profile of the doping concentration in the epitaxial layer is not precisely controlled, it may also cause the threshold voltage to increase. For these reasons, improvement of switching speed cannot easily be accomplished by simply lowering the dopant concentration in the depletion layer. As will be further discussed below, the difficulties are due to the lack of control in depth and width of this low dopant concentration region. Improvements in device switching speed are often provided, in several of prior art device as described below, by degrading other performance characteristics.
In U.S. Pat. No. 5,016,066, entitled xe2x80x9cVertical Power MOSFET having High Withstand Voltage and High Switching Speedxe2x80x9d; Takahashi disclosed a vertical field effect transistor as that shown in FIG. 2 The transistor includes a source electrode and a gate on the front surface of a semi-conductor substrate. The substrate has a first conductivity type and an electrode on the back surface of the substrate. The semiconductor device of has the structure wherein a connection region 3a of the first conductivity type positioned between two channel-forming base regions 4 of a second and opposite conductivity type is formed by a semiconductor layer. The base regions 4 have a higher impurity concentration, eg., p+, than the drain region of the first conductivity type, e.g., nxe2x88x92. The surface portion 3b of the connection region 3a is connected to the channel, which has a lower impurity concentration, e.g., nxe2x88x92, than the connection region 3a, e.g., n+. But the doping concentration is the same as the impurity concentration as the epitaxial layer as that shown in FIGS. 2B and 2C Since tis device is formed to have a structure to provide high withstand voltage, this device is useful for making MOSFET Power device operated at more than 500 volts. For a low voltage device operated below 12 to 60 volts, due to a requirement of low resistivity in the epitaxial layer, the device disclosed by Takahashi tend to have a problem of low switching speed. This is due to a structure that region 3b has a same low impurity concentration as the epitaxial layer. Therefore, the device is not practically useful for low voltage application.
In a Japanese Patent Application 54-132908, entitled xe2x80x9cInsulated Gate Type Field Effect Transistorxe2x80x9d, a transistor field effect transistor is formed to decrease the concentration of an electric field and to increase the dielectric resistance. Referring to FIG. 3 where a gate oxide film is formed on a wall surface of a concave section made up to the drain region. A region that has extremely low concentration of dopant impurities, e.g., nxe2x88x92 region 210, is formed in the drain region at a nose of the concave section. In FIG. 3, an Nxe2x88x92 region 202 functioning as a second drain region is grown on an N+ type semiconductor substrate 201 segregated as a first drain on. An Nxe2x88x92 type region 210 is formed under the groove section 205. The electric field is eased with this extremely low concentration Nxe2x88x92 region. The FET transistor is made to resist high voltage wherein the gate oxide layer is protected near the bottom of the groove. The field effect transistor according to FIG. 3, however may not be practically useful for several reasons. An extremely low concentration region 210 can cause the on-resistance to increase and adversely impact the device performance. Furthermore, an implant operation to form these extremely low concentration regions 210 is not self-aligned. An effort to increase the cell density by reducing the size of the transistor cells is hindered. More lateral distance between cells has to be allowed to accommodate potential misalignment errors.
Therefore, there is still a need in the art of power device fabrication, particularly for power DMOS design and fabrication, to provide a simplified and improved fabrication process that would resolve these limitations. Specifically, a DMOS manufactured by this new method must provided reduced gate-to-drain capacitance to improved the switching speed. In the meantime, improvement of switching speed, provided by the novel device structure and manufacture method, should not be achieved at a price of degrading or sacrificing other design or performance characteristics.
It is therefore an object of the present invention to provide a new and novel MOSFET cell structure, and fabrication process to form a MOSFET device with reduced gate-to-drain capacitance. Reduction of capacitance of the MOSFET device is accomplished without significantly increasing the on-resistance or the threshold voltage whereby the aforementioned limitations encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a new and improved MOSFET manufacture process and cell structure by performing a high energy body-conductivity-type dopant implant, e.g., boron implant, through the gate layer to form a shallow low-doping concentration region, e.g., an nxe2x88x92 region, under the gate. The gate-to-drain capacitance is reduced with reduced doping concentration in the depletion layer under the gate. The switching speed of the device is improved.
Another object of the present invention is to provide a new and improved MOSFET manufacture process and cell structure by performing a high energy body-conductivity-type dopant implant, e.g., boron implant, through the gate layer. A shallow low-concentration region of a source-conductivity-type, e.g., an nxe2x88x92 region, is formed with controllable precision A precisely controllable high-energy implant process can be performed without unduly increasing the on-resistance or the threshold voltage in forming this very shallow low doping concentration region.
Another object of the present invention is to provide a new and improved MOSFET manufacture process and cell structure by performing a high energy body-conductivity-type-dopant implant, e.g., a boron implant through the gate layer. A plurality of shallow low-doping concentration region, e g., nxe2x88x92 regions, are formed after the body diffusion process. The shallow lightly doped region formed in the depletion layer under the gate is prevented from dopant redistribution caused by a long and high temperature body-diffusion process. The dopant profile is more precisely controllable to prevent performance degradation resulting from dopant redistribution due to diffusions.
Another object of the present invention is to provide a new and improved MOSFET manufacture process and cell structure by performing a low-energy light-dose body-dopant implant, e.g., boron implant, via trench openings after a body-diffusion. A plurality of shallow-and-narrow lightly doped source-conductivity-type-dopant regions, e.g., nxe2x88x92 regions, are formed under the trenched gates. The shallow-and-narrow lightly doped region formed under the trenched gate is prevented from dopant redistribution caused by a long and high temperature body-diffusion process. The dopant profile is more precisely controllable to improve the switching speed and to prevent performance degradation resulting from dopant redistribution due to diffusions.
Briefly, in a preferred embodiment the present invention discloses an improved method for fabricating a MOSFET transistor on a substrate to improve the device ruggedness. The fabrication method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an gate oxide layer over the epi-layer; (b) depositing an overlaying polysilicon layer thereon and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the polysilicon mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) performing a high-energy body-conductivity-type-dopant implant, e.g., boron implant, to form a plurality of shallow low-concentration regions of source-conductivity-type, e.g., nxe2x88x92 regions, under each of the gates; (e) applying a source blocking mask for implanting a plurality of source regions in the body regions with ions of the first conductivity type followed by removing the source blocking mask; (e) forming an overlying insulation layer covering the MOSFET device followed by applying a contact mask to open a plurality of contact openings there-through; and (f) performing a low energy body-dopant implant to form a shallow high-concentration second-conductivity-type dopant region followed by applying a high temperature process for densification of the insulation layer and for activating a diffusion of the shallow high-concentration second-conductivity-type dopant regions. A DMOS power device with improved switching speed is provided with reduced gate-to-drain capacitance without causing an increase in either the on-resistance of the threshold voltage.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.